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SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 14, 2001-- Exemplar Logic, a Mentor Graphics Company, today introduced LeonardoSpectrum(TM) 2001.1 (LS 2001.1), the latest version of its market-leading FPGA synthesis tool. LS 2001.1 eases the creation and management of programmable system-on-chip (SoC) designs used in markets such as communications, broadband, wireless and multimedia. In addition, LS 2001.1 delivers enhancements to several Actel device families, new optimization technology for the latest generation Xilinx® Virtex®-II family, new support for Altera's APEX(TM) C and Excalibur(TM) devices, and new support for the Altera encrypted intellectual property (IP) design flow.

Embedding Encrypted IP Made Easy

LS 2001.1 is designed to fit seamlessly with Altera's encrypted IP flow based on the MegaWizard(TM) plug-in design manager. When used with either the MAX_PLUS II® or the new Quartus(TM) II development tools, LS 2001.1 provides a push-button methodology that allows Altera users to easily integrate encrypted IP cores from either the Altera MegaCore(TM) or third-party Altera MegaFunctions Partners Program (AMPPSM) libraries, enabling easy creation of system-on-a-programmable-chip (SOPC) designs.

``Altera is excited about the introduction of LeonardoSpectrum 2001.1. We have worked closely with Exemplar to optimize synthesis results for Altera architectures and to enhance the integration with Altera's new Quartus(TM) II development software,'' said Tim Colleran, vice president of product marketing for Altera. ``LS 2001.1 supports Altera's latest device architectures including the APEX 20KC device family, the Nios(TM) embedded processor core, and the Excalibur ARM-based and MIPS-based embedded processor cores. In addition, this new release includes advanced controls to support Altera's IP Encryption technology, which enables our mutual customers to complete true SOPC designs.''

Push-Button Productivity Enhancements

LS 2001.1 includes several push-button productivity enhancements in its Quick Setup flow. Algorithms have been improved to achieve up to a 2X improvement in run-time. A new graphical slide bar in the flow allows the user to make trade-offs between higher synthesis effort levels and run-time.

The Quick Setup flow in LS2001.1 also offers a new automated design flow for TimeCloser(TM) technology that identifies critical paths after place and route and reoptimizes just those paths by using actual post-place and route timing data. Designers no longer need to manage the files required to run TimeCloser as the Quick Setup flowautomates the process within a push-button environment.

``The breadth and depth of the optimization technology that Exemplar Logic has created are ideal for our new Virtex-II devices,'' said Rich Sevcik, senior vice president and general manager of IP, Services and Software for Xilinx. ``The myriad of features found in LS 2001.1, combined with the flexibility of push-button, incremental, modular, and advanced design flows, gives Virtex-II customers the sophisticated tools they need to achieve high performance and optimal QoR for complex applications, such as digital signal processing (DSP).''

Enhanced Device Support

LS 2001.1 supports the latest devices from FPGA/PLD vendors including support for numerous Actel families, Altera's APEX and Excalibur devices, and Xilinx's Virtex-II family.

Specifics regarding the enhanced device support added to the LS 2001.1 release are listed below.

Actel:

• eX64, eX128, eX256 - Initial device support for the eX low-power family
• RT54SX/SX-S family - Enhanced optimization and timing accuracy as well as new SX-S device support provides high QoR solutions for military and space-based applications where radiation tolerance is required; new TMR (triple mode redundancy) support for SX
• Act2, Act3 families - New TMR and CC (combinatorial cell) support expands support for military and space-based applications
• A54SX/SX-A, A42MX, and 3200DX families - Enhanced optimization and timing accuracy for improved QoR

Altera:

• Expanded Excalibur embedded processor solutions which incorporate the ARM-based and MIPS-based embedded processor cores
• IP encryption technology to support SOPC (system-on-a-programmable-chip) design flow with enhanced capabilities for creating mixed IP core/memory/PLD designs
• Support for the Nios embedded processor as a soft IP core in the encrypted IP flow
• Support for the new APEX 20KC new device family - the first PLD family using all layer copper-interconnect, using advanced APEX device technology mapping for high QoR

Xilinx - Enhanced Virtex II support including:

• Support for all 34 Virtex II devices/speed grades
• Advanced technology mapping to a dedicated high-performance 18x18 multiplier delivers optimal performance and QoR for signed/unsigned multiplication and DSP operations
• Block RAM/ROM and Select RAM(TM)/ROM support - Automatic inference of single and dual-port RAMs; automatic inference of asynchronous and synchronous ROMs
• ClockMUX support - Automatic mapping of clock enables to BUFGCE cell, increasing performance and saving power
• DCM (Digital Clock Manager) support - For multiple clocks in a design, automatically propagates timing constraints to each individual clock
• Advanced Virtex technology mapping carried over from previous release

Price and Availability

LeonardoSpectrum 2001.1 is available immediately. U.S. list price for LS 2001.1 Level 2 starts at $8,950. TimeCloser technology is available in the Level 3 version of the product. U.S. list price starts at $17,500. Supported platforms include Windows® NT, 95, 98 and 2000, Solaris(TM) and HP-UX platforms. LS 2001.1 can also be found in Mentor Graphics FPGA Advantage(TM), which provides designers with a complete FPGA design flow including best-in-class design entry, simulation and synthesis capabilities.

About Exemplar Logic, Inc.

Exemplar Logic, Inc. is a Mentor Graphics Company (Nasdaq:MENT). Exemplar pioneered applying logic synthesis techniques to the design of FPGAs, CPLDs and ASICs. It is the world's number one CPLD and FPGA synthesis tool supplier, as reported by Dataquest. Exemplar's products are sold and supported worldwide by Exemplar Logic, its OEMs and VARs, Mentor Graphics and through the FPGA and CPLD component distribution channel. Exemplar's design environments implement a complete high-level design solution for FPGA, CPLD and ASIC design, offering synthesis, simulation and timing analysis for Windows® 95/98, Windows-NT and UNIX (HP, Sun) platforms in server and non-server environments. Exemplar Logic is located at 880 Ridder Park Drive, San Jose, California 95131. For information on Exemplar representatives or products, please call 408/487-7410, e-mail: sales@exemplar.com, or visit www.exemplar.com.

Exemplar Logic, LeonardoSpectrum, and TimeCloser are trademarks of Mentor Graphics Corp. Windows is a registered trademark of Microsoft Corp. All other company and/or product names are the trademarks and/or registered trademarks of their respective owners.

     Exemplar Logic
     Keri Wilson, 503/685-1359
     keri_wilson@exemplar.com
     or
     Benjamin Group/BSMG Worldwide
     Jason Khoury, 415/352-2628
     jason@benjamingroup.com